Memory diagnostic ROM for Commander X16

Get latest here version 0.4 released 2024/02/22
previous version(s): here

Usage

WARNING: Be very carefull when removing and inserting chips on the Commander X16. The sockets are not necessarily best suited for repeated insertions.

When the ROM boots, the activity LED will indicate the progress of the initial memory test

• ON very briefly while zero pages memory is tested
• OFF while base memory $0100-$9EFF is tested with bit pattern 00000000/11111111
• ON while base memory $0100-$9EFF is tested with bit pattern 01010101/10101010
• OFF while base memory $0100-$9EFF is tested with bit pattern 00110011/11001100
• ON while base memory $0100-$9EFF is tested with bit pattern 00001111/11110000

After the initial test of base memory, the number of memory banks is tested and VERA is initialized to output to VGA.

The main test loop is started and all memory banks are tested with the different bit patterns. If a monitor is connected to the VGA output, it is possible to follow the progress of the tests, but even without a monitor the status can be seen through the activity LED.
In version 0.3 and above the keyboard status LEDs can also be used to monitor the progress of the memory tests. The status LEDs are used in a binary fashion where scroll lock LED is right most bit, caps lock LED is middle bit and num lock LED is left most bit.
The patterns on the keyboard status LEDs are as follows:

• 0 0 1 - Testing RAM banks with 00000000/11111111 pattern
• 0 1 0 - Testing RAM banks with 01010101/10101010 pattern
• 0 1 1 - Testing RAM banks with 00110011/11001100 pattern
• 1 0 0 - Testing RAM banks with 00001111/11110000 pattern
• 1 0 1 - Testing base memory
• 1 1 1 - All tests done, waiting for next pass

A complete pass on a system with 512KB banked memory is about 40 seconds. On a system with 2MB of banked memory the time is about 2 minutes and 10 seconds.

After each pass, the actitivy LED will blink once a second 3 times before continuing with the next pass.
In version 0.3 and above the output mode of VERA toggles between VGA and Composite/S-Vido after each pass.

Error conditions

E$rr:$aaaaTT$pp
| ||  |||||| ||
| ||  |||||| ++--- Test pattern in use when error was detected in hexadecimal form (00, FF, 55, AA, 33, CC, 0F, F0)
| ||  ||||++------ Test type: UP=Test&Replace ascending, DN=Test&Replace desceding, TO=Test Only
| ||  ++++-------- Address in HEX that failed
| ++-------------- RAM bank in use when error was deteced, if applicable, otherwise XX.
+----------------- Error detected

If more than 32 errors are encountered, the test loop stops and the activity LED blinks in the same way as when error is detected before VERA is initialized.

Here is an animation of how it might look, note the red LED at the top right corner which is the activity LED.

Theory

RAM diagnostics are performed with the March C- algorithm. This algorithm should be fairly good at finding most common memory errors.

In short, the algorithm is described as follows:

1. Write 0 to all memory cells
2. For each cell, check that it contains 0 and write 1 in ascending order
3. For each cell, check that it contains 1 and write 0 in ascending order
4. For each cell, check that it contains 0 and write 1 in descending order
5. for each cell, check that it contains 1 and write 0 in descending order
6. Check that all cells contain 0

On the Commander X16 and most other 6502 based computers above algorithm would take a very long time to complete. For this reason the algorithm has been modified slightly to write and compare entire bytes instead of single bits.
To catch most memory errors, the following bit patterns are tested:

• 0000 0000
• 0101 0101
• 0011 0011
• 0000 1111

The algorithm is then implemented in the following way:

1. Write pattern to all memory addresses
2. For each address, check the pattern and write the inverted pattern in ascending order
3. For each address, check the inverted pattern and write the original pattern in ascending order
4. For each address, check the origitnal pattern and write the inverted pattern in descending order
5. For each address, check the inverted pattern and write the original pattern in descending order
6. Check all addresses contain the original pattern

Implementation

The first thing that happens when the ROM boots is that zero-page is tested by it self. If this test passes, the rest of base memory is tested from $0100-$9EFF.

When base memory has passed first test, zero page is used for varables and stack pointer is initialized to enable pushing and popping of registers and function calls.
VERA is initialized and the number of memory banks is tested.

All available memory banks are tested together as opposed to checking and clearing a single memory page at a time.
When all memory banks have been tested, the base memory $0200-$9EFF is tested again.

Memory banks and base memory is tested in a continous loop.

If an error is detected, this is either communicated through the activity LED if VERA has not yet been initialized or by writing information about the error on screen if VERA is initialized.